october 2008 dsc-2964/17 1 ?2007 integrated device technology, inc. features 128k x 8 advanced high-speed cmos static ram commercial (0c to +70c), industrial (?40c to +85c) equal access and cycle times ? commercial and industrial: 12/15/20ns two chip selects plus one output enable pin bidirectional inputs and outputs directly ttl-compatible low power consumption via chip deselect available in 300 and 400 mil plastic soj. functional block diagram description the idt71024 is a 1,048,576-bit high-speed static ram organized as 128k x 8. it is fabricated using idt?s high-performance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs. the idt71024 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. all bidirectional inputs and outputs of the idt71024 are ttl-compat- ible, and operation is from a single 5v supply. fully static asynchro- nous circuitry is used; no clocks or refreshes are required for operation. the idt71024 is packaged in 32-pin 300 mil plastic soj and 32- pin 400 mil plastic soj. address decoder 1,048,576-bit memory array i/o control ? a 0 a 16 2964 drw 01 8 8 i/o 0? i/o 7 8 control logic we oe cs 1 cs 2 cmos static ram 1 meg (128k x 8-bit) idt71024s/ms
6.42 2 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges note: 1. this parameter is guaranteed by device characterization, but is not production tested. truth table (1,2) absolute maximum ratings (1) pin configuration soj top view recommended operating temperature and supply voltage recommended dc operating conditions 5 6 7 8 9 10 11 12 nc a 16 a 14 1 2 3 4 32 31 30 29 28 27 26 25 24 23 22 21 a 15 a 12 a 7 a 6 a 5 a 4 cs 2 a 13 a 8 a 9 a 11 we a 10 2964 drw 02 a 3 13 20 oe 14 19 15 18 16 gnd 17 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v cc cs 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 so32-2 so32-3 notes: 1. h = v ih , l = v il , x = don't care. 2. v lc = 0.2v, v hc = v cc ?0.2v. 3. other inputs v hc or v lc. inputs i/o function we cs 1 cs 2 oe x h x x high-z deselected ? standby (i sb ) xv hc (3 ) x x high-z deselected ? standby (i sb1 ) x x l x high-z deselected ? standby (i sb ) xxv lc (3 ) x high-z deselected ? standby (i sb1 ) h l h h high-z outputs disabled hlhldata out read data llhxdata in write data 2964 tbl 01 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 0.5v. symbol rating value unit v te rm (2) terminal voltage with respect to gnd ?0.5 to +7.0 v t bias temperature under bias ?55 to +125 o c t stg storage temperature ?55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 2964 tbl 02 grade temperature gnd v cc commercial 0c to +70c 0v 5.0v 0.5v industrial ?40c to +85c 0v 5.0v 0.5v 2964 tbl 05 note: 1. v il (min.) = ?1.5v for pulse width less than 10ns, once per cycle. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ___ _ v cc +0.5 v v il input low voltage ?0.5 (1 ) ___ _ 0.8 v 2964 tbl 04 capacitance (t a = +25c, f = 1.0mhz, soj package) symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 8 pf 2964 tbl 03
6.42 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges 3 dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc ? 0.2v) dc electrical characteristics (v cc = 5.0v 10%, commercial and industrial temperature ranges) symbol parameter test condition idt71024 unit min. max. |i li | input leakage current v cc = max., v in = gnd to v cc __ _ 5a |i lo | output leakage current v cc = max., cs 1 = v ih , v out = gnd to v cc __ _ 5a v ol output low voltage i ol = 8ma, v cc = min. __ _ 0.4 v v oh output high voltage i oh = ?4ma, v cc = min. 2.4 __ _ v 2964 tbl 06 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc (all address inputs are cycling at f max ) ; f = 0 means no address input lines are changing. 71024s12 71024s15 71024s20 symbol parameters com'l. ind. com'l. ind. com'l. ind. unit i cc dynamic operating current, cs 2 v ih and cs 1 v il , outputs open, v cc = max., f = f max (2 ) 160 160 155 155 140 140 ma i sb standby power supply current (ttl level) cs 1 v ih or cs 2 v il , outputs open, v cc = max., f=f max (2) 40 40 40 40 40 40 ma i sb1 full standby power supply current (cmos level), cs 1 v hc or cs 2 v lc , outputs open, v cc = max., f = 0 (2 ) , v in v lc or v in v hc 10 10 10 10 10 10 ma 2964 tb l 07 figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) *including jig and scope capacitance. 2964 drw 03 480 ? 255 ? 30pf data out 5v 2964 drw 04 480 ? 255 ? 5pf* data out 5v input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v ac test load see figures 1 and 2 2964 tbl 08 ac test conditions
6.42 4 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges ac electrical characteristics (v cc = 5.0v 10%, commercial and industrial temperature ranges) 71024s12 71024s15 71024s20 symbol parameter min.max.min.max.min.max.unit read cycle t rc read cycle time 12 ? 15 ? 20 ? ns t aa address access time ? 12 ? 15 ? 20 ns t acs chip select access time ? 12 ? 15 ? 20 ns t cl z (1 ) chip select to output in low-z 3 ? 3 ? 3 ? ns t chz (1) chip deselect to output in high-z 0 6 0 7 0 8 ns t oe output enable to output valid ? 6 ? 7 ? 8 ns t olz (1) output enab le to output in low-z 0 ? 0 ? 0 ? ns t ohz (1 ) output disable to output in high-z 050507ns t oh output hold from address change 4 ? 4 ? 4 ? ns t pu (1) chip select to power-up time 0 ? 0 ? 0 ? ns t pd (1) chip deselect to power-down time ? 12 ? 15 ? 20 ns write cycle t wc write cycle time 12 ? 15 ? 20 ? ns t aw address valid to end-of-write 10 ? 12 ? 15 ? ns t cw chip select to end-of-write 10 ? 12 ? 15 ? ns t as address set-up time 0? 0? 0?ns t wp write pulse width 8 ? 12 ? 15 ? ns t wr write recovery time 0? 0? 0?ns t dw data valid to end-of-write 7 ? 8 ? 9 ? ns t dh data hold time 0 ? 0 ? 0 ? ns t ow (1 ) output active from end-of-write 3 ? 3 ? 4 ? ns t whz (1 ) write enable to output in high-z 050508ns 2964 tbl 09 note: 1. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested.
6.42 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges 5 notes: 1. we is high for read cycle. 2. device is continuously selected, cs 1 is low, cs 2 is high. 3. address must be valid prior to or coincident with the later of cs 1 transition low and cs 2 transition high; otherwise t aa is the limiting parameter. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) timing waveform of read cycle no. 2 (1,2,4) address 2964 drw 05 oe cs 1 (5) (5) (5) (5) cs 2 data out valid high impedance t aa t rc t oe t acs t olz t chz t clz (3) t ohz data out t pu t pd vcc supply current icc i sb data out address 2964 drw 06 t rc t aa t oh t oh data out valid previous data out valid
6.42 6 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1,4,6) timing waveform of write cycle no. 2 ( cs 1 and cs 2 controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs 1 , high cs 2 , and a low we . 2. t wr is measured from the earlier of either cs 1 or we going high or cs 2 going low to the end of the write cycle. 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs 1 low transition or the cs 2 high transition occurs simultaneously with or after the we low transition, the outputs remain in a high impedance state. cs 1 and cs 2 must both be active during the t cw write period. 5. transition is measured 200mv from steady state. 6. oe is continuously high. during a we controlled write cycle with oe low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t wp . address cs 1 we cs 2 data out data in 2964 drw 07 (5) (6) (5) (5) data in valid high impedance t wc t aw t as t whz t wp t chz t ow t dw t dh t cw (2) t wr (3) (3) cs 1 address we cs 2 data in 2964 drw 08 t aw t wc t cw t as t wr t dw t dh (2) data in valid
6.42 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges 7 ordering information s power xx speed x package x process/ temperature range blank i commercial (0c to +70c) industrial (?40c to +85c) ty y 300-mil soj (so32-2) 400-mil soj (so32-3) 12 15 20 device type speed in nanoseconds 2964 drw 09 71024 x g restricted hazardous substance device m m current generation die step (optional) first generation or current die step blank
6.42 8 idt71024 cmos static ram 1 meg (128k x 8-bit) commercial and industrial temperature ranges datasheet document history 9/30/99 updated to new format pg. 1, 3, 4, 7 added 12ns industrial speed grade offering pg. 1?4, 7 removed military temperature offerings removed 17ns and 25ns speed grades pg. 3 revised i cc and i sb1 for 15ns and 20ns industrial speed grades pg. 6 removed note 1, reordered notes and footnotes pg. 8 added datasheet document history 1/6/2000 pg. 4 changed t wp (min) for 12ns speed grade from 10ns to 8ns. 2/18/00 pg. 3 revised icc and i sb for industrial temperature offerings to meet commercial specifications 3/14/00 pg. 3 revised i sb to accomidate speed functionaility 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 01/30/04 pg. 7 added "restricted hazardous substance device" to the ordering information. 05/22/06 pg.3 added drawing output capacitive derating drawing. 02/13/07 pg.7 added m generation die step to data sheet ordering information. 10/23/08 pg.7 removed "idt" from the orderable part number. the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com
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